Infineon\Mitchem ddc8fa43f1 Add condition for CurrStage EQ 'PREC' to prevent ...

edge case from Backlog 497 from occuring.

2024-10-23 18:45:23 +02:00

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APPROW

Modified REACT_RUN and RDS to align shift nomenclature

2024-10-10 00:30:56 +02:00

MSG

refactored PTO form to address freezing

2024-09-24 18:44:36 +02:00

OIEVENT

fixed psn and reactor log query forms

2024-09-18 23:39:22 +02:00

OIWIN

Updated ICAR form and commuter module for shift designation changes

2024-10-10 11:42:25 -07:00

POPUP

AdditionalChanges

2024-10-10 00:38:42 +02:00

STPROC

Add condition for CurrStage EQ 'PREC' to prevent

2024-10-23 18:45:23 +02:00

STPROCINS

added fabtime shift calendar

2024-10-07 21:53:20 +02:00